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1-14
Lock-to-Reference Mode
Figure 1-11: Channel PLL Configured as CDR
Channel PLL
LTR/LTD
Controller
Down
Phase
Detector
Up
(PD)
rx_serial_data
/2
SV52002
2014.01.07
Recovered Clock
refclk
/N =
1, 2, 4, 8
(1)
Phase
Frequency
Detector
(PFD)
Up
Down
Charge Pump
&
Loop Filter
Voltage
Controlled
Oscillator
(VCO)
Lock
Detect
/L =
2, 4, 8
(1)
Serial Clock
/rx_is_lockedtodata
/M =
1, 4, 5, 8, 10,
12,16, 20, 25
(1)
Note:
1. Not all combinations of /N, /M, and/L values are valid. The Quartus II software automatically chooses the optimal values.
Lock-to-Reference Mode
In LTR mode, the phase frequency detector (PFD) in the CDR tracks the receiver input reference clock. The
PFD controls the charge pump that tunes the VCO in the CDR. The pma_rx_is_lockedtoref status signal
is asserted active high to indicate that the CDR has locked to the phase and frequency of the receiver input
reference clock.
Note: The phase detector (PD) is inactive in LTR mode.
Lock-to-Data Mode
During normal operation, the CDR must be in LTD mode to recover the clock from the incoming serial
data. In LTD mode, the PD in the CDR tracks the incoming serial data at the receiver input. Depending on
the phase difference between the incoming data and the CDR output clock, the PD controls the CDR charge
pump that tunes the VCO.
Note: The PFD is inactive in LTD mode. The rx_is_lockedtoref status signal toggles randomly and is
not significant in LTD mode.
After switching to LTD mode, the rx_is_lockedtodata status signal is asserted. The actual lock time
depends on the transition density of the incoming data and the parts per million (ppm) difference between
the receiver input reference clock and the upstream transmitter reference clock. The rx_is_lockedtodata
signal toggles until the CDR sees valid data; therefore, you should hold receiver PCS logic in reset
( rx_digitalreset ) for a minimum of 4 μs after rx_is_lockedtodata remains continuously asserted.
Altera Corporation
Transceiver Architecture in Stratix V Devices
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